1. Field of the Invention
The present invention relates to a method and circuit for adaptively processing signals in a digital recording/reproducing apparatus, and more particularly, to a method and circuit for adaptively processing symbol timing recovery and equalization using known signal sequence.
2. Description of the Related Art
In accordance with the development of digital technologies, most conventional analog processing has been replaced by digital signal processing which is stable and widely applicable. Televisions are considerably dependent upon the digital signal processing technology in many aspects and many integrated circuits (ICS) implementing using digital signal processing technology are implemented therein. Like the televisions, video cassette recorders (VCRs) are being digitized and the signal format thereof is digitized but the signal processing thereof is digitized in only limited aspects due to system characteristics of a VCR. In other words, since there are factors varying by interaction between mechanical parts for storing signals onto and reproducing signals from a tape, most signal processing is implemented in an analog format. Since the data used in such a digital VCR is binary data, the digital VCR can be considered a communication system in which signal processing is relatively simplified.
To optimize the sampling timing of an input signal and compensate for variation in frequencies between oscillators of a transmitter and a receiver, the frequencies and phases of clocks of the receiver must be continuously adjusted. Furthermore, timing in a receiver, like that of a digital VCR, must be synchronized to symbols of input data. This is called symbol timing recovery.
For the symbol timing recovery, an open-loop signal processing method and a closed-loop signal processing method can be used. In general, since the performance of a closed-loop structure is better than that of an open-loop structure, the closed-loop structure is mostly used. To obtain a timing phase error, a band edge component maximization (BECM) algorithm using an N-times over-sampling technique is typically used and is disclosed in an article (1) entitled "Passband Timing Recovery in an All-Digital Modem Receiver," D. N. Godard, IEEE Trans. on Communications, vol. COM-26, No. 5, pp. 517-523, May 1978. As another typically used method for obtaining a timing phase error, there has been proposed a Mueller & Muller (to be referred to as "MM" hereinafter) algorithm using symbol timing recovery and symbol rate sampling, which is disclosed in an article (2) entitled "Timing Recovery in Digital Synchronous Data Receivers," K. H. Mueller and M. Muller, IEEE Trans. on Communications, vol. COM-24, No. 5, pp 516-531, May 1976.
FIGS. 1 through 3 show block diagrams of systems implementing methods of possible symbol timing recovery loops. Here, the most simply implemented system is shown FIG. 1, in which a timing detector 12 precedes an equalizer 13, as disclosed in the above-described article (1). In FIG. 1, an analog-to-digital (A/D) converter 11 samples an input signal according to a sampling clock and applies the sampled data to the timing detector 12 and equalizer 13. The timing detector 12 detects a timing phase error from the sampled data and supplies the sampling clock for compensating for the phase error to the A/D converter 11. The equalizer 13 equalizes the sampled data. Therefore, the timing detector 12 shown in FIG. 1 is not affected by the equalizer 13. This is an over-sampling method in which the sampling clock requires an N-times symbol frequency.
FIG. 2 shows a structure in which an equalizer precedes a timing detector, as disclosed in the above-described article (2). In FIG. 2, an analog-to-digital (A/D) converter 21 samples an input signal according to a sampling clock and an equalizer 22 equalized the sampled data output from the A/D converter 21. The timing detector 23 detects a timing phase error from the equalized data output from the equalizer 22 and applies the sampling clock for compensating for the phase error to the A/D converter 21. Thus, the equalizer 22 shown in FIG. 2 is a fractionally spaced equalizer. Therefore, even if symbol timing recovery is not completely performed, the equalizer 22 serves as an interpolator for performing timing error detection from an inter-symbol interference (ISI) eliminated signal output from the equalizer 22, thereby reducing timing jitter. However, in this case, signal processing speed must be increased. Also, in the case of a serious noise, the equalizer 22 may not operate properly due to misconvergence caused by an initial timing error.
According to the systems shown in FIGS. 1 and 2, the hardware becomes complex since a timing phase error signal detected by a voltage controlled oscillator (VCO) built in the timing detectors 12 and 23 must be supplied for detecting sampling positions of the A/D converters. To overcome such a drawback, a system shown in FIG. 3 is used to implement a perfect digital receiver, which is disclosed In an article (3) entitled "Interpolation in Digital Modems--Part I: Fundamentals," Floyd M. Gardner, IEEE Trans. on Communications, vol. COM-41, No. 3, pp. 501-507, March 1993.
In FIG. 3, an analog-to-digital (A/D) converter 31 samples an input signal using the clock of a fixed oscillating frequency generated from a fixed VCO 32 as a sampling clock. An interpolator 33 interpolates the sampled data output from the A/D converter 31 and applies the interpolated data to a timing detector 34 and an equalizer 36. A timing detector 34 detects a timing phase error from the interpolated data. A controller 35 generates a clock for the interpolation of the interpolator 33 for the purpose of controlling the phases of the sampled data. The equalizer 36 equalizes the interpolated data.
According to the system shown in FIG. 3, A/D conversion is performed with a fixed clock and sampling is performed by adjusting the phases of the interpolator 33, thereby generating a symbol timing recovered signal. Although the method implemented in the system shown in FIG. 3 also requires an over-sampling technique, the sampling frequency can be easily implemented by performing A/D conversion at a sampling rate slightly higher than that of a symbol clock frequency.
A DVCR requires a fast signal processing of a symbol rate higher than or equal to 40 MHZ. Thus, it is quite difficult to apply the symbol timing recovery method using the over-sampling technique practically to the DVCR. Even if it is possibly applied thereto, the product becomes expensive. However, for fast system initialization, the DVCR initially transmits to the respective tracks prescribed symbols, which can be used as training sequence. Thus, since the MM algorithm operates optimally when training sequences are given, it is advantageous to adopt the MM algorithm for symbol timing recovery.
Also, an equalizer for a DVCR operates mainly for correcting the waveform of pulses, rather than for eliminating multipath noise. The equalizer for a DVCR has a relatively shorter filter tap length (about 5 taps) and higher sampling frequency (about 40 MHZ), compared to an equalizer used for terrestrial broadcasting in a conventional television. Thus, since it is difficult to accomplish fractional equalizing structures necessitating over sampling, there has been an increasing demand for an adaptive equalizer.